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High speed filtering using reconfigurable hardware Resumen: This research develops a real-time implementation of computationally expensive prediction filters by means of task parallelization and task segmentation methodologies in an FPGA. There is a brief description of the prediction filter, then two types of implementations have been developed: PC-based sequential implementations using MATLAB and C++; and an FPGA-based parallelized implementation using VHDL. A comparative study between both types of implementations shows that the execution times measured on the FPGA are considerably lower, making this implementation valid for applications with real-time requirements. Experimental results are shown for a visual servoing task to illustrate the good performance of the proposed algorithms and implementations. |